library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity REG is
   port(CLK,LD_Reg: in bit; --LD_Reg: in std_logic; 
        DR, SR2: in unsigned(3 downto 0); 
        Reg_In: in unsigned(15 downto 0);
        ReadReg1, ReadReg2,ReadReg3,ReadReg4: out unsigned(15 downto 0));
end REG;
architecture Behavioral of REG is
   type RAM is array (0 to 15) of unsigned(15 downto 0);

   signal Regs: RAM := (
   "0000000000000011",--0 R0 = 3
   "0000000000000010",--1 R1 = 2
   "0011111100000000",--2
   "1011101000000000",--3 R3 = xBA00
   --"0101010101010101",--3
   "1010101010101010",--4
   "1111000011110000",--5
   "0000111100001111",--6
   "0000000000101010",--7
   "0000000000001100",--8
   "0000000000000000",--9
     others => (others => '0'));  -- set all reg bits to '1'

begin
   process(LD_Reg,DR,SR2,Reg_In, CLK)
   begin
      if CLK = '1' and CLK'event then
         if LD_Reg = '1' then Regs(to_integer(DR)) <= Reg_In; end if;
      end if;
   
   end process;
  ReadReg1 <= Regs(to_integer(DR)); --asynchronous read
  ReadReg2 <= Regs(to_integer(SR2)); --asynchronous read
  ReadReg3 <= Regs(3); --result register
  ReadReg4 <= Regs(0); --loop counter
end Behavioral;